1. Statement of the Technical Field
The inventive arrangements relate to wireless networks. More particularly, the present invention relates to a method and apparatus for high speed protocol header processing at an intermediate and/or destination node of a packet-based communications network.
2. Description of the Related Art
There has been a growing demand for improved communication applications provided by packet-based communications networks. The phrase “packet-based communications network” as used herein refers to an internet protocol (IP) based communications network and a transmission control protocol/internet protocol (TCP/IP) based communications network. As a result the growing demand, a header processing approach has been employed to improve the abilities of the packet-based communications networks. The header processing approach includes the transmission of packets including signaling protocol data and/or application data between nodes of the packet-based communications networks. The application data can include voice data, video data, or the like. The nodes can be selected as a computer system, a routing device, a sensor, a battery powered wireless communications device, or any other device having a TCP/IP based packet interface.
To enable the transmission of packets between a set of nodes, the application data is encapsulated between one or more protocol stack layer headers and a frame check sequence (FCS). The phrase “frame check sequence” as used herein refers to extra checksum characters added to a packet or a frame in a communication protocol for error detection and correction. In this regard, it should be understood that a checksum is a form of a redundancy check. A checksum protects the integrity of data by detecting errors in the data that are sent through space or time.
For example, the application data is encapsulated between an application layer header (or protocol header) and the frame check sequence (FCS). The application layer header is encapsulated between a transport layer protocol header and the application data. The transport layer protocol header is encapsulated between a network layer protocol header and the application layer header. The network layer protocol header is encapsulated between a logic link control (LLC) layer protocol header and the transport layer protocol header. The logic link control (LLC) layer protocol header is encapsulated between a media access control (MAC) layer protocol header and the network layer protocol header. The media access control (MAC) layer protocol header is encapsulated between a physical layer protocol header and the logic link control (LLC) protocol header. The physical layer protocol header is encapsulated between a preamble and the media access control (MAC) layer protocol header. As should be understood, the encapsulation framework depends on the network's protocol model, such as an open system interconnection model or a Department of Defense protocol model. The protocol headers are comprised of fields to be processed at intermediate and/or destination nodes. Some protocol headers have long fields that require a comparison among several values. As such, a packet transmission often experiences relatively long delays due to protocol header processing at intermediate and/or destination nodes.
Many solutions have been proposed for decreasing the protocol header processing time at intermediate and/or destination nodes of a packet-based communications networks. One such solution employs a sequential processing approach. The sequential processing approach involves receiving an encoded packet at a node, decoding the received encoded packet, and processing protocol headers of the decoded packet in a sequential manner. In this regard, it should be noted that the sequential processing approach is dependent on methods to advance the protocol header processing from one protocol header to a next protocol header. This solution is based on either specialized processors configured for processing a particular protocol header and/or a general purpose central processing unit (CPU).
More specifically, the sequential processing approach includes the following steps: (1) receive a packet at an intermediate and/or a destination node; (2) decode the received packet at a physical layer processor; (3) process a preamble and a physical layer protocol header of the decoded packet at the physical layer processor; (4) sequentially write a media access control (MAC) layer protocol header, a logic link control (LLC) layer protocol header, a network layer protocol header, a transport layer protocol header, an application layer header, and an application data to a packet buffer memory for storage; (5) access the packet buffer memory and retrieve the media access control (MAC) layer protocol header therefrom; (6) process the media access control (MAC) layer protocol header at a media access control (MAC) layer processor; (7) access the packet buffer memory and retrieve the logic link control (LLC) layer protocol header therefrom; (8) process the logic link control (LLC) layer protocol header at a logic link control (LLC) layer processor; (9) access the packet buffer memory and retrieve the network layer protocol header therefrom; (10) process the network layer protocol header at a network layer processor; (11) access the packet buffer memory and retrieve the transport layer protocol header therefrom; (12) process the transport layer protocol header at a transport layer processor; (13) access the packet buffer memory and retrieve the application layer header therefrom; and (14) process the application layer header at an application layer processor. Despite the advantages of the sequential processing approach, it suffers from certain drawbacks. For example, the majority of protocol header processing tasks are implemented in software as generic packet processing methods.
Another such solution employs fixed function applications specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). Despite the advantages of such fixed function devices, they suffer from certain drawbacks. For example, the fixed function devices cannot handle updating processing header fields. Further, the fixed function devices always defer protocol header processing to a general purpose processor. The general purpose processor cannot operate at a desired speed for a battery powered wireless communications device. The general purpose processor also cannot accommodate changes in timing needs due to high speed, very high bandwidth data traffic.
In view of the forgoing, there is a need for a solution to reduce protocol header processing time in a packet-based communications networks. This solution also needs to be configured to update header fields. The solution further needs to be configured to process protocol headers at a desired speed for a battery powered wireless communications device. In this regard, it should be understood that a battery powered wireless communications device can be a node in a high speed wireless communications system. As such, the battery powered wireless communications device can concurrently act as an intermediate node and a destination node. As such, the roles of the battery powered wireless communications device can alternate and vary based on time or traffic conditions.